A second drawback of a pure device is that it does not filter any redundant state changes 純?cè)O(shè)備的第二個(gè)缺點(diǎn)是它不會(huì)濾除任何冗余狀態(tài)變化。
To avoid the idleness state and the corresponding power dissipation in sequential circuits , a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation 為抑制時(shí)序電路中的冗余現(xiàn)象,研究了時(shí)序電路的門控時(shí)鐘技術(shù),并利用t型觸發(fā)器進(jìn)行時(shí)序電路設(shè)計(jì)。